Cache operations using transformed indexes
US8595441B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Oct 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for reducing the likelihood of cache line overlaps in a multi-processor system having a shared memory cache. A transformation function module coupled to the shared memory cache is configured to transform an index associated with a cache operation associated with a processor of the plurality of processors using a transformation function to generate a transformed index. In embodiments, groups of one or more processors have different or unique transformation functions associated with them in order to decrease the tendency or likelihood of their respective cache lines in the shared memory cache to overlap. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.