Method and apparatus for verifying memory testing software
US8595557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.