Quasi-cyclic low-density parity-check codes
US8595589B2 · kind B2 · utility
8Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and a method for determining a quasi-cyclic (QC) low-density parity-check (LDPC) code, such that the QC LDPC code has no trapping sets are disclosed. A set of matrices representing a family of QC LDPC codes are acquired, wherein each QC LDPC code is a tail-biting spatially-coupled code of girth not less than eight, and wherein each column of each matrix in the set has a weight not less than four. Based on a trapping set pattern, a matrix from the set of matrices is selected such that the matrix represents the QC LDPC code with no trapping sets. The matrix can be stored into a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.