Methods of performing error detection/correction in nonvolatile memory devices
US8595601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Dec 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.