Method and apparatus for circuit block reconfiguration EDA
US8595670B1 · kind B1 · utility
3Cited by
11References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Aug 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.