Low-power FPGA circuits and methods
US8595671B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of Vdd, multiple voltage thresholding Vt, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi Vdd FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.