Validating interconnections between logic blocks in a circuit description
US8595678B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Feb 3, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | May 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.