Constrained random error injection for functional verification
US8595680B1 · kind B1 · utility
11Cited by
0References
30Claims
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Key dates
| Filing date | Jun 15, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, a method may include simulating a memory circuit, wherein the memory circuit is configured to store data. The method may also include receiving, by the simulated memory circuit, a memory access operation. The method may further include dynamically determining, in response to the memory access, if, based on a set of predefined criteria, the simulated memory circuit should generate a memory error as the result of the memory access. The method may also include, if the simulated memory circuit is to generate the memory error, generating the memory error as the result of the memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.