Timestamping logic with auto-adjust for varying system frequencies
US8598910B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Aug 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.