Frequency-locked synthesizer with low power consumption and related system and method
US8598924B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.