Hybrid impedance compensation in a buffer circuit
US8598941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2011 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/447
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.