Nonvolatile semiconductor memory
US8599613B2 · kind B2 · utility
415Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jun 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/702
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.