Network protocol header alignment
US8599855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.