QR-RLS adaptive digital filter with 18-bit pipeline architecture
US8599903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2220/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A QR-RLS adaptive digital filter provides fast computation without excessive computational resources. 18-bit multipliers enhance speed, and a floating point inverse square root block adjusts dynamic range in 12-dB steps. A memory stores two P-matrix copies, one being delivered with rows shifted according to the clock speed so as to enhance pipeline processing. Embodiments reliably detect modulation schemes, demodulate strong signals by passing feedback bits between multiple stages, remove impulses due to lightening, etc, erase symbol estimates which exceed an error threshold, and add high frequency noise to avoid mathematical divergence caused by excessive S/N. A genetic method is provided for identifying asynchronous spreading codes with minimum correlations, whereby randomly selected candidates compete based on Frobenius norms of their correlations, the weakest being discarded and the process being iterated. A method is provided for selecting optimal filter sampling windows for simultaneously detected symbol streams having relative timing delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.