Maintaining required ordering of transaction requests in interconnects using barriers and hazard checks
US8601167B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2010 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device and includes at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to the recipient device; at least one path for transmitting the transaction requests between the input and the output; and control circuitry for routing the received transaction requests from the input to the output, wherein the control circuitry is configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along one of the paths, by not allowing reordering of at least some of the transactions requests that occur before the barrier transaction request in the stream of transaction requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.