Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC
US8601302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jun 5, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.