Method of circuit design yield analysis
US8601416B2 · kind B2 · utility
50Cited by
3References
22Claims
0Family size
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Key dates
| Filing date | Jun 28, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.