Instruction-by-instruction checking on acceleration platforms
US8601418B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | May 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.