Intergrated circuit having latch circuits and using delay to fetch data bits in synchronization with clock signals
US8601427B2 · kind B2 · utility
6Cited by
13References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Dec 3, 2013 |
| Priority date | — |
| Expiry date | Jan 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.