Method for fabricating super-junction power device with reduced miller capacitance
US8603879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2013 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | May 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.