Multi-gate field-effect transistor with enhanced and adaptable low-frequency noise
US8604549B2 · kind B2 · utility
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Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.