Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
US8604603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Aug 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.