Dual-trigger low-energy flip-flop circuit
US8604855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2013 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jun 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.