Calibrating timing, gain and bandwidth mismatch in interleaved ADCs
US8604953B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.