Timing calibration circuit for time-interleaved analog-to-digital converter and associated method
US8604954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC) is provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.