Read only memory device with complemenary bit line pair
US8605480B2 · kind B2 · utility
4Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2011 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Dec 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.