Multilevel nonvolatile semiconductor memory system
US8605500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2011 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y<x) based on x bits, transferring y bit to the memory, and generating 2y threshold distributions based on y bit in the memory, and a second step executing after the first step, transferring x bits to the memory, and generating the 2x threshold distributions based on x bits in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.