Tracking capacitive loads
US8605523B2 · kind B2 · utility
168Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.