Adaptive frequency synthesis for a serial data interface
US8605846B2 · kind B2 · utility
1Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | May 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.