Edge detection apparatus and computing circuit employed in edge detection apparatus
US8606016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/10024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An edge detection apparatus includes a computing circuit and a determining circuit. The computing circuit includes a first multiplier block and a first adder unit. The first multiplier block includes n×m first multiplier units, wherein each first multiplier unit has a first multiplication factor. The n×m first multiplier units respectively perform multiplications on n×m pixels which are arranged as an n×m matrix to generate n×m first product values based on the corresponding first multiplication factors. The n×m pixels include a target pixel, where n is not equal to m. The first adder unit generates a first computation result according to the n×m first product values. The determining circuit determines if the target pixel is an edge pixel according to at least the first computation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.