N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module
US8606842B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Aug 21, 2008 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Oct 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.