Barrier transactions in interconnects
US8607006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2010 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Dec 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.