Patent · US Active

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

US8607129B2 · kind B2 · utility

17Cited by

1References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sivakumar Radhakrishnan · Portland, US
Mark A. Schmisseur · Phoenix, US
Sin S. Tan · Portland, US
Kenneth C. Haren · Portland, US
Thomas C. Brown · Portland, US
Pankaj Kumar · Barwala, IN
Vinodh Gopal · Westborough, US
Wajdi K. Feghali · Boston, US

Key dates

Filing date	Jul 1, 2011
Grant date	Dec 10, 2013
Priority date	—
Expiry date	Apr 17, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6575
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.