Load detecting impedance matching buffer
US8610456B2 · kind B2 · utility
3Cited by
6References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.