Differential delay cell with low power, low jitter, and small area
US8610478B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay cell architecture is provided herein with improved noise performance and increased output swing, while consuming less power and area than conventional delay cell architectures. In one embodiment, the delay cell described herein may include a pair of input transistors, a pair of cross-coupled transistors, a pair of current source transistors, at least one swing limiting transistor and an RC filter. The at least one swing limiting transistor is coupled between the output nodes of the delay cell for controlling the output swing and keeping the current source transistors in saturation. Phase-induced jitter is reduced by connecting the RC filter directly to the mutually-coupled source terminals of the current source transistors. Deterministic jitter is reduced by using a relatively large resistor and relatively small capacitor within the RC filter design. Such a design reduces the amount of area consumed by the delay cell without sacrificing noise performance. Current consumption is reduced by requiring only one bias voltage to be supplied to the delay cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.