True time delay circuits including archimedean spiral delay lines
US8610515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P9/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.