Circuits and methods for hardening volatile memory circuits through one time programming
US8611138B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2012 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and techniques for operating a memory cell on an integrated circuit (IC) are disclosed. A disclosed memory cell includes a first inverter coupled to a second inverter to form a first connection and a second connection. The first connection is operable to receive at least a first data signal at a first voltage and the second connection is operable to receive at least a second data signal at a second voltage. A first oxide capacitor and a second oxide capacitor are coupled to the first and second connections respectively. Both the first and second oxide capacitors are coupled to receive a programming signal at a third voltage that may be operable to rupture either one of the first or second oxide capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.