Device and method to perform memory operations at a clock domain crossing
US8611178B2 · kind B2 · utility
1Cited by
22References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 11, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.