Systems, methods and apparatus for superconducting demultiplexer circuits
US8611974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2009 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/92
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.