Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic
US8612500B2 · kind B2 · utility
2Cited by
4References
14Claims
0Family size
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Key dates
| Filing date | Jan 14, 2008 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4912
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.