Minimum resource fast fourier transform
US8612505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2009 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A minimum resource FFT design may calculate the FFT for an input data series using minimal logic resources to implement the FFT. In one implementation, the FFT design may include a butterfly component for performing one or more complex addition and multiplication operations and outputting a plurality of results; a first memory coupled to the butterfly component, the first memory including a number of memory banks equal in number to the number of the plurality of the results; a second memory coupled to the butterfly component, the second memory including a number of memory banks equal in number to a number of the plurality of the results; and a control component to control reading and writing from the first and second memories and the butterfly component using a ping-pong access technique that reads and writes intermediate values to the first and second memories to implement the FFT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.