Memory management process and apparatus for the same
US8612664B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jul 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer (400) and a second data object consumer (410); b) arranging a address translation process for mapping the real address of an object to be stored within said banks into the address of the bank; b) receiving one object produced by said producer and dividing it into stripes of reduced size; c) storing the first stripe into said first bank; d) storing the next stripe into said second bank while the preceding stripe is read by said object consumer (410); e) storing the next stripe into said first bank again while the preceding stripe is read by said object consumer (410). f) repeating e) and c) until all stripes composing said data objects have been processed; g) arranging an interlocking mechanism for locking the writing and reading process in said banks to ensure producer has enough space to for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.