Method and system for managing a NAND flash memory by paging segments of a logical to physical address map to a non-volatile memory
US8612666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.