Memory controller connection to RAM using buffer interface
US8612684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2007 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jan 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.