Deep idle mode
US8612786B1 · kind B1 · utility
10Cited by
11References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Sep 27, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During deep idle mode, a root clock such as the microcontroller unit phase-locked loop (MPLL) is scaled or gated entirely and other clocks such as the processor, memory, and general purpose timer clocks may be scaled. To maintain functionality while these clocks are scaled or gated, an external clock source couples to the processor, memory, and a general purpose timer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.