System and method for improving wear-leveling performance in solid-state memory
US8612804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Sep 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that need to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a rule-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the rule-based approach, wear leveling is periodically triggered by a specified interval of erase counts associated with a unit of solid-state memory such as a group of blocks, rather than by a threshold based on erase counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.