Apparatus, system, and method for decoding linear block codes in a memory controller
US8612834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1545
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.