Configurable integrated tamper detection circuitry
US8613111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2011 |
| Grant date | Dec 17, 2013 |
| Priority date | — |
| Expiry date | Jan 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tamper detection circuitry includes a first surface layer surrounding a protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section by a plurality of conductive traces, the programmable interconnect being configured to group the conductive section of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; and a tamper detection module, the tamper detection module configured to detect tampering in the event that a conductive section that is part of a first circuit comes into physical contact with a conductive section that is part of a second circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.