Method for fabrication of interconnect structure with improved alignment for semiconductor devices
US8614144B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Nov 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.