Hybrid successive approximation analog-to-digital converter
US8614638B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Jul 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.